Sps: a Strategically Programmable System
نویسندگان
چکیده
We are presenting a novel reconfigurable system architecture: the Strategically Programmable System (SPS). The motivation for such a system is the needs of today’s high flexibility, high performance computing. SPS contains versatile blocks embedded into fully reconfigurable logic. Dedicated blocks fixed on the chip perform the bulk of the computations; hence the reconfiguration time of the system is highly improved as well other performance metrics such as speed and power consumption. Fine grain reconfigurable logic helps maintain high flexibility.
منابع مشابه
An Fpga Based Multiprocessing Cpu for Beam Synchronous Timing in Cern’s Sps and Lhc
The Beam Synchronous Timing system (BST) will be used around the LHC and its injector, the SPS, to broadcast timing messages and synchronize actions with the beam in different receivers. To achieve beam synchronization, the BST Master card encodes messages using the bunch clock, with a nominal value of 40.079 MHz for the LHC. These messages are produced by a set of tasks every revolution period...
متن کاملReal-Time Expansion of Software Programmable Logic Controllers
Fuji Electric is providing “SPS” as a software PLC (programmable controller) for the “MICREX-SX” series of integrated controllers. The SPS is a PLC operated on Windows NT*1, a general-purpose OS (operating system) for the PC (personal computer), and is well received because it shares the same programming language and development environment as the hardware PLC for the MICREX-SX. Realization of ...
متن کاملAn FPGA-based High Speed Parallel Signal Processing System for Adaptive Optics Testbed
In this paper a state-of-the-art FPGA (Field Programmable Gate Array) based high speed parallel signal processing system (SPS) for adaptive optics (AO) testbed with 1 kHz wavefront error (WFE) correction frequency is reported. The AO testbed consists of Shack-Hartmann sensor (SHS) and deformable mirror (DM), tip-tilt sensor (TTS), tip-tilt mirror (TTM) and an FPGA-based high performance SPS to ...
متن کاملDesign and Implementation of Field Programmable Gate Array Based Baseband Processor for Passive Radio Frequency Identification Tag (TECHNICAL NOTE)
In this paper, an Ultra High Frequency (UHF) base band processor for a passive tag is presented. It proposes a Radio Frequency Identification (RFID) tag digital base band architecture which is compatible with the EPC C C2/ISO18000-6B protocol. Several design approaches such as clock gating technique, clock strobe design and clock management are used. In order to reduce the area Decimal Matrix C...
متن کاملField Programmable Gate Array–based Implementation of an Improved Algorithm for Objects Distance Measurement (TECHNICAL NOTE)
In this work, the design of a low-cost, field programmable gate array (FPGA)-based digital hardware platform that implements image processing algorithms for real-time distance measurement is presented. Using embedded development kit (EDK) tools from Xilinx, the system is developed on a spartan3 / xc3s400, one of the common and low cost field programmable gate arrays from the Xilinx Spartan fami...
متن کامل